This paper presents a digital implementation of the Selective Harmonic Elimination Pulse-Width Modulation Technique (SHE-PWM) using a FPGA (Field Programmable Gate Array) with its logical structure developed through the VHDL language. A theoretical study of harmonics elimination strategy is detailed and as experimental results are shown the gate signals provided by the FPGA, which validate the digital development of the technique together with simulation of that strategy. The technique is applied to a five level hybrid multilevel inverter based on the Half-Bridge and ANPC topologies. DIGITAL IMPLEMENTATION OF SHE-PWM MODULATION ON FPGA FOR A MULTILEVEL INVERTER