SMART CONTROLLER BOARD FOR POWER ELECTRONICS APPLICATION.
SPECIFICATION:
• Modified Harvard architecture
• C compiler optimized instruction set architecture
• 84 base instructions with flexible addressing modes
• 24-bit wide instructions, 16-bit wide data path
• 12 Kbytes on-chip Flash program space
• 512 bytes on-chip data RAM
• 1 Kbyte non-volatile data EEPROM
• 16 x 16-bit working register array
• Up to 30 MIPs operation:
– DC to 40 MHz external clock input
– 4 MHz-10 MHz oscillator input with
PLL active (4x, 8x, 16x)
• 27 interrupt sources
• Three external interrupt sources
• 8 user selectable priority levels for each interrupt
• 4 processor exceptions and software traps.
DSP Engine Features:
• Modulo and Bit-Reversed modes
• Two, 40-bit wide accumulators with optional saturation logic
• 17-bit x 17-bit single cycle hardware fractional/integer multiplier
• Single cycle Multiply-Accumulate (MAC)operation
• 40-stage Barrel Shifter
• Dual data fetch
Peripheral Features:
• High current sink/source I/O pins: 25 mA/25 mA
• Three 16-bit timers/counters; optionally pair up
16-bit timers into 32-bit timer modules
• Four 16-bit Capture input functions
• Two 16-bit Compare/PWM output functions
– Dual Compare mode available
• 3-wire SPITM modules (supports 4 Frame modes)
• I2CTM module supports Multi-Master/Slave mode and 7-bit/10-bit addressing
• Addressable UART modules with FIFO buffers Motor Control PWM Module Features:
• 6 PWM output channels
– Complementary or Independent Output modes
– Edge and Center Aligned modes
• 4 duty cycle generators
• Dedicated time base with 4 modes
• Programmable output polarity
• Dead time control for Complementary mode
• Manual output control
• Trigger for synchronized A/D conversions