Description
High-Performance Modified RISC CPU:
- Modified Harvard architecture
- C compiler optimized instruction set architecture
- 84 base instructions with flexible addressing modes
- 24-bit wide instructions, 16-bit wide data path
- 12 Kbytes on-chip Flash program space
- 512 bytes on-chip data RAM
- 1 Kbyte non-volatile data EEPROM
- 16 x 16-bit working register array
- Up to 30 MIPs operation.
- DC to 40 MHz external clock input
- 4 MHz-10 MHz oscillator input with
- PLL active (4x, 8x, 16x)
- 27 interrupt sources
