0431-4340778, 07639385448 [email protected]


In this paper, a PWM scheme for three-level full-SiC uninterruptible power supplies (UPSs) has been developed to achieve a high power-density. Two key passive components have been selected for size reduction of the full-SiC UPS; common mode (CM) EMI filter and dc-link capacitors. To reduce the CM noise, a new vector combination has been proposed based on a synchronous switching of three-phases. The proposed combinations align CM voltage (CMV) to be a single pulse per a switching period. CMV cancellation between a three-level rectifier and inverter can be maximally utilized while a drift of neutral point voltage can be prevented by transition among three combinations. Secondly, to reduce dc-link capacitors, a simple algorithm to compensate neutral point voltage fluctuation has been proposed both for differential-and common-mode output voltage. The proposed algorithm can simply be implemented by a correction on carrier-slopes and injected zero-sequence voltage. The proposed scheme has been verified with 20 kW full-SiC UPS switching at 60 kHz with 146 F dc-link capacitors. Single Pulse Common-Mode Voltage PWM Scheme to Achieve High Power-Density for FullSiC Three-level Uninterruptible Power Supply